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TS-4200 Manual

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Documentation from May-2010


Table of Contents

1 Introduction

2 TS-4200 Specific Features

3 TS-4200 Pinouts

Appendix A: Environmental Specifications

Appendix B: Further References

Appendix C: Revision History


1 Introduction

1.1 About this Manual

This manual is intended to provide the user with an overview of the TS-SOCKET Macrocontroller series, its benefits, and only the feature specifications which are unique to the TS-SOCKET Macrocontroller. This manual serves as the complement to the TS-SOCKET Manual.

1.2 Feedback and Update to this Manual

To help our customers make the most of our products, we are continually making additional and updated resources available on the Technologic Systems website at http://www.embeddedarm.com.

These include manuals, application notes, programming examples, and updated software and firmware. Check in periodically to see what's new!

When we are prioritizing work on these updated resources, feedback from customers (and prospective customers) is the number one influence. If you have questions, comments, or concerns about your Embedded Computer, please let us know at support@embeddedarm.com.

1.3 Limited Warranty

Technologic Systems warrants this product to be free of defects in material and workmanship for a period of one year from date of purchase. During this warranty period Technologic Systems will repair or replace the defective unit in accordance with the following process:

A copy of the original invoice must be included when returning the defective unit to Technologic Systems, Inc. This limited warranty does not cover damages resulting from lightning or other power surges, misuse, abuse, abnormal conditions of operation, or attempts to alter or modify the function of the product.

This warranty is limited to the repair or replacement of the defective unit. In no event shall Technologic Systems be liable or responsible for any loss or damages, including but not limited to any lost profits, incidental or consequential damages, loss of business, or anticipatory profits arising from the use or inability to use this product.

Repairs made after the expiration of the warranty period are subject to a repair charge and the cost of return shipping. Please, contact Technologic Systems to arrange for any repair service and to obtain repair charge information.

1.4 FCC Advisory Statement

This equipment generates, uses, and can radiate radio frequency energy and if not installed and used properly (that is, in strict accordance with the manufacturer's instructions), may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class A computing device in accordance with the specifications in Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the owner will be required to correct the interference at his own expense.

If this equipment does cause interference, which can be determined by turning the unit on and off, the user is encouraged to try the following measures to correct the interference:

  • Reorient the receiving antenna.
  • Relocate the unit with respect to the receiver.
  • Plug the unit into a different outlet so that the unit and receiver are on different branch circuits.
  • Ensure that mounting screws and connector attachment screws are tightly secured.
  • Ensure that good quality, shielded, and grounded cables are used for all data communications.
  • If necessary, the user should consult the dealer or an experienced radio/television technician for additional suggestions.

The following booklets prepared by the Federal Communications Commission (FCC) may also prove helpful:

  • How to Identify and Resolve Radio-TV Interference Problems (Stock No. 004-000-000345-4)
  • Interface Handbook (Stock No. 004-000-004505-7)

These booklets may be purchased from the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402.

1.5 Software and Support

Technologic Systems provides:

  • Free system software and documentation updates available on our web site
  • Free technical support by phone, fax, or email
  • 30-day, money back guarantee on evaluation units
  • One-year, full warranty
  • Linux OS Support

1.6 Conventions Used

Filenames and code statements are presented in Courier.

   Similarly, code blocks or sections better suited for
   plain text display, such as example terminal output, 
   are presented in indented preformatted text.

Commands issued by the reader are indicated in bold Courier. New terms or important concepts are presented in italics.

When you see a pathname preceded with three dots, this references a well-known but unspecified top-level directory. The top-level directory is context dependent but almost universally refers to a top-level Linux source directory. For example, .../arch/arm/kernel/setup.c refers to the setup.c file located in the architecture branch of a Linux source tree. The actual path might be something like ~/sandbox/linux.2.6.21/arch/arm/kernel/setup.c.

Hardware interfaces, such as pin numbers or names, are described by ALL CAPS.

NOTE:

Text appearing in this manner offers notes and/or comments that will aid in your understanding.

WARNING:

Text appearing in this manner offers a warning. You can make a mistake here that hurts your system or is hard to recover from.

1.7 TS-SOCKET Series

The TS-SOCKET standard is an embedded computer standard designed and controlled by Technologic Systems, Inc. It defines both a form factor and a connection pin-out and is based on two 100-pin low-profile connectors, allowing secure connection between a TS-SOCKET Macrocontroller (CPU board) and a baseboard. Please refer to the TS-SOCKET Standard and Embedded Macrocontrollers resource for more information.

1.8 TS-ARM Development Kit

The TS-ARM Development Kit for the TS-SOCKET series includes all equipment necessary to boot into the operating system of choice and start working. The development kit is highly recommended for a quick start on application development. For example, the TS-ARM Development Kit for the TS-4200 (KIT-4200) includes:

  • Development 2GB microSD with ECLIPSE IDE and USB microSD card reader (MSD-2GB-USB-4200)
    • Debian Linux 5.0 (Lenny) Distribution compiled for ARM
    • Full tool-chains (uclibc and glibc) for cross compiling for ARM
    • Utility source code (ie. sdctl.c) and example programs
  • TS-8200 development platform including low cost plastic enclosure (TS-ENC820)
  • Regulated DC power supply and all cables including NULL Modem cable, etc.

NOTE:

Single board computer is not included in the Development Kit (sold separately).

1.9 Product Overview

The TS-4200 is a low power TS-SOCKET Macrocontroller board based on the Atmel AT91SAM9G20 ARM9 running at 396 MHz. The TS-4200 features 10/100 Ethernet, high speed USB host and device, MicroSD card, and 256 MB XNAND drive. For basic usage, please refer to the TS-SOCKET Manual. This document covers features that are specific to the TS-4200.

1.10 Benefits

Out-of-the-Box Productivity

Technologic Systems Linux products get you to your application quickly. Our Single Board Computers boot directly to Linux as shipped. There is no complicated CMOS setup or configuring of a Linux derivative Operating System to source, define, and load. A Technologic Systems SBC user can power up the board and immediately begin application development.

Of course, should you wish to configure your own version of Linux or use a different operating system, this is easy too. Technologic Systems provides the solution to fast application development without tedious OS configuration.

Low Power with High Performance

The TS-4200 was designed to offer the end user with a product that consumes very little power while still providing high computing performance. The TS-4200 represents one of the highest power to performance ratios in the Technologic Systems product line.

Small Form Factor

The TS-4200 is nearly the same size as a credit card which gives it an advantage when being considered for an application with very tight space limitations or constrictions. Mating high density connectors (available from the TS-4200 website) make it easy for you to design a baseboard or connection system that brings out only the features of the TS-4200 that you need which can further help you squeeze the TS-4200 into your application.

Future Ready

Modularity is the focus with the TS-SOCKET standard. Baseboards designed for one TS-SOCKET Macrocontroller will have high, drop-in compatibility with future release of another TS-SOCKET Macrocontroller. With this, you don't need to be concerned about being locked into one particular design, giving your application leg room to grow.

A Plethora of External Connections

The TS-SOCKET Macrocontrollers offer many connections and buses via the high density connectors, such as GPIO, SPI, I2C, I2S, that give the TS-SOCKET Macrocontrollers the added benefit of being able to interact with external peripherals and sensors.

Talk with Engineers Directly

At Technologic Systems, our Embedded Systems Engineers answer to both support requests as well as sales inquiries. If you have any questions about the TS-SOCKET standard, Linux kernel or distribution, baseboard layout, or just questions, they are here to help.

1.11 Features

The TS-4200 can run at a full 396 MHz while consuming under half a Watt. The following features help meet this goal:

  • Efficient switching regulators
  • Low power Atmel CPU that can disable clocks to any of its peripherals
  • Low power Actel FPGA clocked by the CPU only when needed
  • Low power 1.8V mobile RAM
  • Ethernet and SD card that can be disabled to save power

TS-4200 hardware features include:

  • Atmel AT91SAM9G20 CPU running at 396 MHz
  • 64 MB or 128 MB low power SDRAM
  • Actel A3P125 FPGA (3072 tiles, 4KB SRAM)
  • 256 MB XNAND drive storage
  • Ethernet MAC and PHY
  • 2 USB host (12 Mbps) and 1 USB device (480 Mbps).
  • Up to 6 UARTs (1 Auto-485 capable)
  • microSD card connector (or external full size SD)
  • SPI
  • I2C
  • I2S
  • 4 ADC inputs
  • RTC*
  • 8KB NV SRAM *
  • Up to 78 DIO/GPIO **
  • Temperature Sensor ***
  • Watchdog timer
  • Random number generator
NOTE:

* External coin cell battery required.

** Depends on features used (I2C, I2S, SPI, UARTs, etc). If all features are used, 39 GPIO are still available. Note: DIO pins marked with PC4-10 and PC13-14 on schematic are 1.8V logic level whereas all others are 3.3V logic level.

*** 1/16 of degree Celsius resolution (and 1 degree absolute accuracy).

1.12 Configurability

The TS-4200 can be ordered with either 64 MB or 128 MB DDR-RAM configurations. Part numbers are TS-4200-64-256XF and TS-4200-128-256XF respectively. No other on-board configurations are available.

2 TS-4200 Specific Features

The purpose of this chapter is to provide Technologic Systems TS-4200 customers with information that is specific and unique to their board which keeps documentation clean and concise with only relative material. For general documentation not specific to the TS-4200, refer to the TS-SOCKET Manual which includes topics such as general Linux usage, connectors and interfaces information, and generic Technologic Systems utilities. For example, the following features are discussed in the TS-SOCKET manual and not in this document: Ethernet, USB, XNAND, and SPI.

2.1 Bootup

The TS-BOOTROM on the TS-4200 supports two boot media: XNAND flash and SD card. Like other TS-SOCKET modules, XNAND is the default boot and SD boot can be forced by grounding the MODE2 line, pin 98 on CN1. XNAND boot is recommended for an ultra-reliable boot mechanism.

2.2 Standard Utilities and Shell Functions

The ts4200ctl (TS-4200 control) utility is installed by default on the TS-4200. Run ts4200ctl --help for a list of supported features. Source code for this program is available on our ftp site and serves as sample code demonstrating how to access various hardware features, including FPGA DIO, NVRAM, RTC, I2C, LEDs, and the watchdog timer.

In addition, the file /ts4200.subr is a shell function file which is sourced by default. The functions in this file demonstrate many of the board's features.

2.3 microSD Card

On the TS-4200, SD card access is supported in the default kernel. After the mmc drivers are installed, the SD card appears as /dev/mmcblk0.

2.4 FPGA

The Actel FPGA is connected to the SMC bus on CS0 and CS2. Configuration registers for the SMC bus are set by the bootrom and should not be modified. Chip select 2 is used for 16 bit access and chip select 8 is used for 8 bit access. 16 bit access on CS 2 is recommended for most uses. The FPGA memory map is as follows:

Offset Function
0x0 System Controller
0x100 NAND registers
0x200 NVRAM control registers
0x400 External bus address space (not currently implemented)
0x800 Direct blockram access (for NVRAM data)

The FPGA is not continuously clocked. The FPGA clock is driven by CPU pin PB31 which is a timer counter output. When PB31 is configured for peripheral B, it will thus output a 49.5 MHz waveform which is what the FPGA expects and uses for a global clock. When no dynamic FPGA features are being used, pin PB31 can be switched to an input to stop clocking the FPGA and save power.

The system controller memory map is as follows: (all 16 bit registers)

   base + 0x0: board id register.  Reads 0x4200 on TS-4200
   base + 0x2: submodel, fpga revision, DIO and LED control - (R/W)
     bit 15: green LED (1 - on)
     bit 14: red LED (1 - on)
     bit 13-8: reserved
     bit 7-4: board submodel (RO) - 0x0 on production TS-4200
     bit 3-0: FPGA revision
   base + 0x4: DIO direction for DIO 15(MSB)-0(LSB)
   base + 0x6: DIO output data for DIO 15(MSB)-0(LSB)
   base + 0x8: DIO input data for DIO 15(MSB)-0(LSB)
   base + 0xa: TS-4200 control register
     bits 15-11: reserved
     bit 10: TX enable enable (1 - use DIO12 for uart0 TXEN instead of DIO)
     bit 9: 512 Hz enable (1 - use 512 Hz for WDT instead of 200 Hz)
     bit 8: reset switch enable (1 - auto reboot when dio_i[9] == 0) (RW)
     bit 7-6: reserved
     bit 5: mode2 strap input (RO)
     bit 4: mode1 strap input (RO)
     bit 3: reserved
     bit 2: enable ethernet power
     bit 1: enable SD card power
     bit 0: off-board reset signal
   base + 0xc: 32-bit 1 MHz free running counter (16 LSBs)
   base + 0xe: 32-bit 1 MHz free running counter (16 MSBs)
   base + 0x10: watchdog feed register
     write value 0x0: feed watchdog for another 0.5 sec
     write value 0x1: feed watchdog for another 2 sec
     write value 0x2: feed watchdog for another 16 sec
     write value 0x3: disable watchdog
   base + 0x12: DIO direction for DIO 31(MSB)-16(LSB)
   base + 0x14: DIO output data for DIO 31(MSB)-16(LSB)
   base + 0x16: DIO input data for DIO 31(MSB)-16(LSB)
   base + 0x18: RNG LSB
   base + 0x1a: RNG MSB
   base + 0x1c: embedded FlashROM access
     bit 15: FlashROM clock
     bits 14-8: FlashROM address
     bits 7-0: FlashROM data
   base + 0x1e: UART0 baud rate divisor (for auto 485 txen)

Not all bits in the DIO register are connected to pins. See the Pinouts chapter for more details.

The watchdog timer continues to run even when the FPGA is not clocked. For a clock, it either uses a 512 Hz signal coming from the RTC or a ~200 Hz signal coming from an external RC oscillator. Which of these is used depends on TS-4200 control register bit 9. When the board powers on, the watchdog is enabled by default and it is controlled by the 200 Hz input. The RTC 512 Hz signal is then enabled by the startup script.

For many applications, the watchdog timer can be fed in the background by ts4200ctl --autofeed.

32 bits of random data are available once per second from the RNG registers. This random data is created in the FPGA by comparing the asynchronous 49.5 MHz and 200 Hz clock signals.

The FPGA contains embedded FlashROM. As the name suggests, data in the FlashROM cannot be modified. It is used to store the board's Ethernet MAC address and born-on date. In order to read the FlashROM, write a valid FlashROM address, toggle the FlashROM clock, and then read the data. This is demonstrated by ts4200ctl.c source code.

If UART 0 is used for RS-485, DIO_12 (CN1 pin 67) can be used to drive the TXEN signal. To do this, set bit 10 of the TS-4200 control register to 1, and set the UART0 baud rate divisor to the same value that is set in the Atmel serial baud rate divisor. The FPGA will then monitor the TXD line and set TXEN correctly.

2.5 NVRAM

The 8KB non-volatile SRAM requires an external battery that provides 3.3V on the V_BAT pin. When 5V power is not available, V_BAT is used to power the NVRAM as well as the real time clock.

The NVRAM control memory map is as follows:

   0x0: status register
     bit 0: busy flag.  Indicates transfer is occurring.
     bit 1: power fail.  1 = further transfers are not permitted.
     bits 15-2: reserved
   0x2: control register (Do not modify while busy flag is set.)
     bit 0: 1 = copy blockram to NVRAM | 0 = copy NVRAM to blockram
     bits 2-1: NVRAM bank used for copy
     bits 15-3: reserved
   0x4: enable register (bit 0 only, RW)
   0x6: Power fail flag can be cleared by writing 0 to this register.

The NVRAM can not be written directly by the CPU. Data is moved between the NVRAM chip and FPGA blockram in 2KB blocks. To perform a transfer to or from the NVRAM, first set up the control register accordingly, then set the enable register. Then poll the busy flag until it is busy, and then clear the enable register. The busy flag will be 1 until the transfer is complete. To make a small modification to NVRAM contents, it is necessary to do a read-modify-write of the 2KB block. NVRAM access is demonstrated by ts4200ctl.c source code.

The FPGA blockram is read or written in the 2KB window beginning at 0x30000800.

The NVRAM core also monitors the POWER_FAIL# input. Transfers to NVRAM cannot be initiated after a power fail has been detected. If the power fail signal occurs in the middle of a block transfer, the transfer will be completed and then no further transfers will occur. The transfer takes 1.33ms, so a baseboard that provides a power fail signal with a 1.33ms cushion before the 5V rail collapses can guarantee NVRAM data integrity.

2.6 GPIO

Some GPIO pins on the TS-4200 are driven by the FPGA as described above. Many others are driven by the CPU. The CPU driven pins are those labeled PA0-PA31, PB0-PB31, and PC0-PC31, but only 39 of these are available for external GPIO. The setdiopin and getdiopin functions in ts4200.subr demonstrate how these can be used. These pins can be used for peripherals or GPIO. Pin PB31 is a notable exception. The pin labeled PB31 on the TS-4200 schematic, CN2 pin 56, is actually FPGA DIO 31. CPU GPIO PB31 is connected to the FPGA clock input, as described above. To control the external pin from the shell, use setdiopin 31 0|1|z not setdiopin pb31...'

2.7 Serial Ports

Aside from the debug port, the TS-4200 has six serial ports, designated UART0 to UART5. UART0 is RS-485 capable as described above. Any serial ports not needed by your application can be used for DIO.

2.8 ADC

The AT91 CPU includes four ADC channels. The getadc function in ts4200.subr demonstrates how these can be used. A reference voltage must be provided on the VREF input. The getadc function assumes a 3.3V reference voltage.

3 TS-4200 Pinouts

All offboard connections on the TS-4200 TS-SOCKET Macrocontroller module go through the 2 high density 100 pin board to board connectors CN1 and CN2. The mating connectors and mechanical layout specification are available from the TS website.

Left Connector (CN1)

Pin # Name Function Pin # Name Function
1 FPGA_JTAG_TMS JTAG int0erface for FPGA, 4.7k pull up 2 EXT_RESET# Input used to reboot TS-4500
3 FPGA_JTAG_CLK JTAG interface for FPGA, 4.7k pull up 4 EN_USB_5V USB 5V enable output
5 FPGA_JTAG_TDO JTAG interface for FPGA 6 SDCARD_D2 SD data bus, in parallel with onboard SD
7 FPGA_JTAG_TDI JTAG interface for FPGA, 4.7k pull up 8 SDCARD_D3 SD data bus, in parallel with onboard SD
9 OFF_BD_RESET# Off board reset output, asserted when board boots or reboots 10 SDCARD_CMD SD command IO, in parallel with onboard SD
11 BOOT_OVERRIDE ??? 12 SDCARD_3.3V SD card power
13 SPIO_CLK ??? 14 SDCARD_CLK SD card clock
15 POWER Board 5V power 16 POWER Board 5V power
17 POWER_FAIL# ??? 18 SDCARD_D0 SD data bus, in parallel with onboard SD
19 Unconnected 20 SDCARD_D1 SD data bus, in parallel with onboard SD
21 Unconnected 22 SER_FLASH_WP# ???
23 Unconnected 24 Unconnected
25 Unconnected 26 Unconnected
27 Unconnected 28 Unconnected
29 POWER Board 5V power 30 Unconnected
31 Unconnected 32 Unconnected
33 Unconnected 34 Unconnected
35 Unconnected 36 V_BAT RTC Battery voltage
37 Unconnected 38 Unconnected
39 Unconnected 40 Unconnected
41 Unconnected 42 Unconnected
43 Unconnected 44 Unconnected
45 Unconnected 46 Unconnected
47 POWER Board 5V power 48 Unconnected
49 Unconnected 50 Unconnected
51 Unconnected 52 Unconnected
53 Unconnected 54 Unconnected
55 Unconnected 56 Unconnected
57 Unconnected 58 Unconnected
59 Unconnected 60 Unconnected
61 Unconnected 62 GND Ground
63 DIO_14 DIO, XUART#2 TXEN, FPGA weak pull-up 64 MUX_AD15 External Databus
65 DIO_13 DIO, XUART#1 TXEN, FPGA weak pull-up 66 MUX_AD14 External Databus
67 DIO_12 DIO, XUART#0 TXEN, FPGA weak pull-up 68 MUX_AD13 External Databus
69 DIO_11 DIO, XUART#6 RX, FPGA weak pull-up 70 MUX_AD12 External Databus
71 DIO_10 DIO, XUART#6 TX, FPGA weak pull-up 72 MUX_AD11 External Databus
73 DIO_9 DIO, reset switch input (active low), FPGA weak pull-up 74 MUX_AD10 External Databus
75 GND Ground 76 MUX_AD09 External Databus
77 DIO_8 DIO, FPGA weak pull-up 78 MUX_AD08 External Databus
79 DIO_07 DIO, FPGA weak pull-up 80 MUX_AD07 External Databus
81 DIO_06 DIO, FPGA weak pull-up 82 MUX_AD06 External Databus
83 DIO_5 DIO, FPGA weak pull-up 84 MUX_AD05 External Databus
85 DIO_4 DIO, FPGA weak pull-up 86 MUX_AD04 External Databus
87 DIO_3 DIO, FPGA weak pull-up 88 MUX_AD03 External Databus
89 DIO_2 DIO, FPGA weak pull-up 90 MUX_AD02 External Databus
91 DIO_1 DIO, FPGA weak pull-up 92 MUX_AD01 External Databus
93 DIO_0 DIO, FPGA weak pull-up 94 MUX_AD00 External Databus
95 GND Ground 96 BUS_ALE# ???
97 BUS_WAIT# ??? 98 BUS_RD# ???
99 BUS_BHE# ??? 100 BUS_WR# ???
NOTE:

SD card signals on connector are wired in parallel with SD card socket. Only one can be populated with an SD card.

Right Connector (CN2)

Pin # Name Function Pin # Name Function
1 ETH_RX+ 10/100 Ethernet RX+ 2 ETH_LEFT_LED Ethernet jack left LED
3 ETH_RX- 10/100 Ethernet RX- 4 ETH_RIGHT_LED Ethernet jack right LED
5 ETH_CT Ethernet center tap 6 RED_LED# Red led output
7 ETH_TX+ 10/100 Ethernet TX+ 8 GREEN_LED# Green led output
9 ETH_TX- 10/100 Ethernet TX- 10 SHUT_DOWN ???
11 ETH_CT Ethernet center tap 12 WAKE_UP ???
13 Unconnected 14 CPU_RESET# ???
15 Unconnected 16 PC0 ???
17 Unconnected 18 PC1 ???
19 Unconnected 20 PC2 ???
21 GND Ground 22 PC3_SPI_CS3# ???
23 DEV_USB_M Device USB port 24 AN_VREF ???
25 DEV_USB_P Device USB port 26 PA22 ???
27 1.0V_BU ??? 28 TW_CLK DIO, CPU connected I2C SCL, 4.7k pull-up
29 HOSTA_USB_M Host USB port A 30 TW_DAT DIO, CPU connected I2C SDA, 4.7k pull-up
31 HOSTA_USB_P Host USB port A 32 PA6 ???
33 Loop 1.0V 2.5V power (output from module) 34 NAND_WP# ???
35 HOSTB_USB_M Host USB port B 36 PB16 I2S
37 HOSTB_USB_P Host USB port B 38 PB17 I2S
39 3.3V 3.3V power (output from module) 40 PB18 I2S
41 Unconnected 42 PB19 I2S
43 Unconnected 44 CPU_JTAG_TMS CPU JTAG interface
45 GND Ground 46 CPU_JTAG_TCK CPU JTAG interface
47 Unconnected 48 CPU_JTAG_TDI CPU JTAG interface
49 Unconnected 50 CPU_JTAG_TDO CPU JTAG interface
51 GND Ground 52 PB29 ???
53 Unconnected 54 PB27 ???
55 Unconnected 56 PB26 ???
57 1.8V 1.8V power (output from module) 58 PB25 ???
59 Unconnected 60 PB21 ???
61 Unconnected 62 PB22 ???
63 1.5V 1.5V power (output from module) 64 PB20 ???
65 SPI_CS0# SPI CS0#, weak FPGA pull-up 66 PB31 ???
67 SPI_MOSI SPI master-out slave-in (output from module) 68 PB30 ???
69 SPI_MISO SPI master-in slave-out (input to module) 70 PB28 ???
71 SPI_CLK SPI clock (output from module) 72 PB24 ???
73 GND Ground 74 PB23 ???
75 PC4_SPI_CS2# ??? 76 Unconnected
77 PC5_SPI_CS1# ??? 78 PA31 Serial Ports ???
79 PC6 1.8V Level CPU DIO 80 PA30 Serial Ports ???
81 PC7 1.8V Level CPU DIO 82 PB4 Serial Ports ???
83 PC8 1.8V Level CPU DIO 84 PB5 Serial Ports ???
85 PC9 1.8V Level CPU DIO 86 PB6 Serial Ports ???
87 PC10 1.8V Level CPU DIO 88 PB7 Serial Ports ???
89 PC13 1.8V Level CPU DIO 90 PB8 Serial Ports ???
91 PC14_IRQ2 ??? 92 PB9 Serial Ports ???
93 DEBUG_TXD Serial console TX (TTL output) 94 PB10 Serial Ports ???
95 DEBUG_RXD Serial console RX (TTL input) 96 PB11 Serial Ports ???
97 DIO_15 DIO, CAN bus TXD, fpga weak pull-up 98 PB12 Serial Ports ???
99 DIO_16 DIO, CAN bus RXD, fpga weak pull-up 100 PB13 Serial Ports ???
NOTE:

Ethernet Magnetics should be placed as close to CN2 as possible on the baseboard.

Appendix A: Environmental Specifications

To ensure optimum product operation you must maintain the operational environmental specifications:

  • Ambient Temperature: -40° to +85° C
  • Relative Humidity: 0 to 90% relative humidity. Not to exceed 90% non-condensing.
NOTE:

Contact Technologic Systems if the environmental temperature of the location is in doubt.

Appendix B: Further References

Appendix C: Revision History

Date of Issue/Revision Revision Number Comments
05/13/2010 1.0 Released as TS-4200 Manual