Table of Contents
- Getting Started
- SD card features
- Board Specific features
The TS-7350 is a compact, flexible, affordable single board computer running Linux 2.6 out of the box.
Hardware features include:
- 200 MHz ARM9 CPU
- PC/104 connector
- Up to 128MB DDR-RAM
- 5,000 LUT FPGA
- 10/100 Ethernet
- SD socket
- dual USB2.0 Full-Speed
- On-board framebuffer
Software features include:
- Unbrickable design
- Backward-compatible with TS-72xx boards
- Boots Linux in under 2 seconds
- Linux 2.6 and Debian
The TS-7350 is based on the Cirrus EP9302 Processor, which implements ethernet, USB, and two UARTs. For technical information on these functions please refer to the Cirrus user manual. The TS-7350 also utilizes a Lattice XP2 FPGA. Please refer to datasheets available from Lattice for more information.
The TS-9445 development console board (included in the development kit) is required for development with the TS-7350. Attach the TS-9445 to the JTAG header on the TS-7350, connect the 10 pin header COM adapter to the TS-9445, and use that to connect to your development PC with a DB9 cable. Boot messages followed by a linux prompt should be displayed through the console.
The TS-7350 boot mechanism requires a bootable SD card. If you did not purchase an SD card with your board, you can create a factory SD card using any 512MB or larger SD card. An SD card image is available here. When power is applied with the SD card inserted, the default boot behavior is fastboot, which provides a busybox prompt in under 2 seconds. When this shell is exited the board continues on to perform a full Debian boot. This behavior is controlled by the linuxrc script, which by default is a symbolic link to linuxrc-fastboot. To automatically boot full Debian, link it instead to linuxrc-sdroot. Please note that changes made to files on the initial ramdisk are saved only in RAM. To save your changes permanently, type "save" at the fastboot prompt.
The SD cards shipped with and for the TS-7350 contain a special four partition scheme. The first partition is a VFAT partition. On cards larger than 1GB, this partition contains Eclipse and other tools, documentation, and so forth. On cards smaller then 1GB this partition is empty. The second partition contains a raw image of the kernel to be booted on the board, while the third partition contains an initial ramdisk (initrd) which the kernel uses as its root filesystem until the fastboot shell exits. The fourth partition contains the Debian Linux distribution, and contains the root filesystem that is used when the fastboot shell exits and the full boot commences.
There are three LEDs on the TS-7350: one red, one green, and one yellow. The green LED comes on at power-up and stays on by default. The green and red LEDs are controlled through the CPU GPIO port E. They can be controlled using bits 0 and 1 of the port E register at address 0x8084_0020. The yellow LED is controlled by bit 6 of the register at 0x600ff084.
The TS-7350 has a built-in true random number generator (RNG). The number is generated from internal random entropy. The 32-bit value at address 0x600f_f0d0 contains the most recent random value generated. Only thirty-two bits of true random data are created every second, so if this register is read more quickly the values read are not guaranteed to be random: in fact, you will either read the same value as previously or else a pseudo-random intermediate value from the last value generated.
The general header is a 40 pin (2x7, 0.1" spacing) header providing I2C, SPI, GPIO, latched outputs, buffered inputs, A/D inputs, an external reset line, and a console UART.
The general header is made up of two adjacent headers, labeled JTAG and DIO:
The pins on the 40 pin header serve a variety of functions. Refer to the table below to see which pins are available for each functionality.
|JTAG 3||GND||Tied to ground|
|JTAG 9||SPI_MISO||SPI bus|
|JTAG 10||3.3V||Tied to 3.3V|
|JTAG 12||SPI_MOSI||SPI bus|
|JTAG 14||SPI_CLK||SPI bus|
|JTAG 15||5V||Tied to 5V|
|JTAG 16||EXT_RESET#||External reset|
|DIO 1||SPI_FRAME||SPI bus|
|DIO 2||GND||Tied to ground|
|DIO 4||OUT_5||Latched output|
|DIO 5||IN_00||Buffered input|
|DIO 6||OUT_4||Latched output|
|DIO 7||IN_01||Buffered input|
|DIO 8||OUT_3||Latched output|
|DIO 9||IN_02||Buffered input|
|DIO 10||OUT_2||Latched output|
|DIO 11||IN_03||Buffered input|
|DIO 12||OUT_1||Latched output|
|DIO 13||IN_04||Buffered input|
|DIO 14||OUT_0||Latched output|
|DIO 15||IN_05||Buffered input|
|DIO 17||IN_06||Buffered input|
|DIO 20||ADC2||ADC/Buffered input|
|DIO 22||ADC1||ADC/Buffered input|
|DIO 24||ADC0||ADC/Buffered input|
Please note:Pins labeled "reserved" are used at the factory for production purposes and should not be used for applications.
Pins labeled ADC are available for analog to digital conversion using the Cirrus 5 channel A/D converter. Channels 0, 1, 2, and 4 are available for applications. Channel 3 is used internally.
Each of these pins, if not being used for A/D conversion, can instead be used as a buffered input, or in the case of pin DIO 16, a GPIO pin. For instructions on that please refer to the relevant section below.
Pins labeled "DIO" are connected directly to EP9302 GPIO pins. To use these pins, you must first set the data direction registers, and then read or write values from the data registers. When accessing these registers, it is important to do a read-modify-write, as other bits may be used internally. Pins labeled BGPIO are accessed through port B. The port B data direction register is located at address 0x80840014 and the port B data register is at 0x80840004. Pins labeled HGPIO are accessed through port H. The port H data direction register is located at address 0x80840044 and the port H data register is at 0x80840040.
There are a total of 10 buffered digital input lines. Pins IN_0 through IN_6 are dedicated digital inputs, while pins IN_9 through IN_11 are in parallel with analog inputs and thus can only be used for digital input if analog inputs are not needed. Pins IN_0 through IN_3 have resistor pull-ups. The others will return random data if not driven high or low.
The 32 bit register at address 0x600f_f084 provides access to digital inputs. Pins IN_0 through IN_6 are accessed by bits 7 through 13. Pin IN_9 is accessed by bit 15. Pins IN_10 and IN_11 are accessed by bits 27 and 28.
Pins OUT_0 through OUT_5 are digital output lines. The 32 bit register at address 0x600f_f084 provides access to digital outputs through bits 0 through 5.
UART0_TXD and UART0_RXD bring out the TTL level signals from the CPU. By default, this UART provides boot messages and the Linux console.
The SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_FRAME pins bring out the SPI bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.
The I2C_SCL and I2C_SDA pins bring out the I2C bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.
Driving the external reset pin low will reset the CPU. While the JFS file system on the SD card is extremely resilient and is normally not damaged by hard resets, rebooting the board using the reboot command is still recommended if the file system is mounted read/write.
The temperature sensor is accessed via SPI pins on the DIO header documented in the previous section. The DATA pin on the TMP124 is connected to the SPI_MISO# signal, while the CLK pin is connected to the SPI_CLK pin. In addition there is a chip select signal which must be asserted in order to use the temperature sensor chip. This signal is accessed through bit 2 of the register at address 0x80840030. (CPU GPIO port F) Note that the polarity of this signal is active high (set this bit to select the temp sensor).
The PC-104 connector consists of 64 pins in two rows labeled A and B. The numbering of the pins in each row is shown below:
The PC-104 connector can be multiplexed between different functionalities including ISA bus and GPIO. The power-up default is GPIO mode, with all I/Os in a neutral state. To enable the PC-104 bus (ISA) signals, it is necessary to write the following values to the registers specified:
0x55555555 to address 0x600ff09c
More specifically, the functionality of the PC-104 connector can be configured in a more fine-grained manner, two pins at a time. Each pin pair will have one of four functions:
Setting the function of each pair of pins is done by writing the function number to the appropriate pair of bits in the register corresponding to the row in question. The table below shows the bit positions in each register on the top row, while the cells below in the same column give the corresponding pin numbers for each row which are programmed with those bits at the specified register address.
For example, from the above table we can see that to set the function of pins B19 and B20 we would write the function number to bits [19:18] of the register at address 0x600ff09c. We can tell this because when we look at the "B" row we see "20 19" in the cell whose column is headed by "19 18".
The function of the PC-104 connector pins are given in the table below. The "ISA" column gives the name of the pin signal when it is configured as ISA, while the "GPIO" column gives the name of the pin signal when it is configured as GPIO. To save space, there are two sets of columns in each table, whereby the pin name is listed first, followed by the ISA signal and then the GPIO signal, and then this order is repeated for the other set of pins
Note: The GPIO nomenclature in these tables is such that, for example, "A" means "Bit 0 of GPIO Register A", and in general "X[n]" means "Bit n of GPIO Register X" and "X[n:m]" means "Bits n through m of GPIO register X", where X is one of A or B.
The TS-7350 provides control over some of the ISA parameters of the PC-104 bus through a 32-bit register located at address 0x600ff0d4, which is defined as follows:
|5-0||ISA strobe length|
|9-6||ISA setup length|
|10||Honor ISA 0WS/ENDX signal (1=true)|
|11||TS special ISA pinout enable (1=true)|
|12||ISA oscillator select
(Other bits in this register should be masked out.)
The ISA strobe length and ISA setup length are both given as the number of extra 10ns periods.
The ISA strobe length is the amount of additional time that ISA_IOR, ISA_IOW, ISA_MEMR, and ISA_MEMW are held asserted. The minimum (when bits are zero) is 20ns. The default power-on value is 40, for a 420ns strobe length. If configured to honor the ISA 0WS/ENDX signal, the peripheral will skip the remaining strobe time for an early transaction end, allowing for faster devices than standard ISA allows.
The ISA setup length is the additional amount of time above 20ns that the address and data are held stable before asserting the strobe. The default is 14 (160ns).
There is an additional 20ns hold time at the end of the strobe where address and data are kept valid. The default total bus cycle length is then 160ns (setup) plus 420ns (strobe) plus 20ns (hold) for a total of 500ns (2Mhz). This is very conservative for modern hardware and most designs can actually run much faster.
Pc/104 peripherals will appear in the TS-7350's physical address space in one of two address regions, depending on whether it is emulating an x86 memory cycle or I/O cycle. The base address for I/O cycles is 0x600ff800. The base address for memory cycles is 0x60002000.
The PC-104 connector can be multiplexed between PC-104 functionality and GPIO functionality. There are up to 56 general purpose digital I/O pins available. This corresponds to 64 pins total minus 8 pins carrying power or ground rails.
Each GPIO pin has a two corresponding register bits, one in the GPIO data register, and one in the GPIO direction register. The direction register determines if the pin is an output (actively driven) or an input (tri-stated, driven externally). A high ("1") value sets a particular pin to be an output, while a low ("0") value sets it to be an input. The data register, when read, contains the current state of all pins in GPIO mode. When written, the value written will determine the state of all pins in GPIO mode, but only for pins which have their direction set to "output".
The GPIO register map follows:
The TS-7350 incorporates 7 XUARTs implemented in the FPGA.
Under Linux, these are accessed through /dev/ttzn where n is the XUART # (from the table
below). The device driver name is xuart7350. To use
the UARTs on the PC104 bus, the pins must be set to GPIO
functionality. When these ports are closed, the GPIO
functionality is used; when the ports are open the UART functionality
overrides the GPIO functionality.
||Tx / X+
||Rx / X-
(*) Bit 14 of the 16-bit register at 0x600FF0D4 must be set to
enable Rx on this pin.
The appropriate RS-485 option (OP-485-FD-12 or OP-485-FD-14) must be purchased with the board to use the RS-485 ports. In full-duplex RS-485 mode, the pins for TS-UART #4 are used for Rx on TS-UART #3. To set RS-485 Full Duplex, set bit 6 of the register at address 0x600ff086.
Important Note: Due to time constraint, the TS-7350/TS-7370 boards were released while the XUART design was still in development. Because of this, some boards (those born before October 1, 2008) do not have the necessary firmware to support the XUART. There are two options to remedy this: one is to return the board to have the firmware updated. The other is to download the TS-7350/TS-7370 bitstream with XUART support and load the bitstream during the boot process. There is a writeup on considerations for loading a bitstream that can assist in this process.
The latest version of the XUART driver is available on the ftp site. Please note that this is a beta version with a few known performance issues that we are currently working to resolve.
- 08.12.2008: Created
- 12.17.2008: XUART #3 X+/X- were backwards