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Table of Contents

Introduction

The TS-7350 is a compact, flexible, affordable single board computer running Linux 2.6 out of the box.

Hardware features include:

  • 200 MHz ARM9 CPU
  • PC/104 connector
  • Up to 128MB DDR-RAM
  • 5,000 LUT FPGA
  • 10/100 Ethernet
  • SD socket
  • dual USB2.0 Full-Speed
  • On-board framebuffer

Software features include:

  • Unbrickable design
  • Backward-compatible with TS-72xx boards
  • Boots Linux in under 2 seconds
  • Linux 2.6 and Debian

The TS-7350 is based on the Cirrus EP9302 Processor, which implements ethernet, USB, and two UARTs. For technical information on these functions please refer to the Cirrus user manual. The TS-7350 also utilizes a Lattice XP2 FPGA. Please refer to datasheets available from Lattice for more information.

Getting Started

The TS-9445 development console board (included in the development kit) is required for development with the TS-7350. Attach the TS-9445 to the JTAG header on the TS-7350, connect the 10 pin header COM adapter to the TS-9445, and use that to connect to your development PC with a DB9 cable. Boot messages followed by a linux prompt should be displayed through the console.

The TS-7350 boot mechanism requires a bootable SD card. If you did not purchase an SD card with your board, you can create a factory SD card using any 512MB or larger SD card. An SD card image is available here. When power is applied with the SD card inserted, the default boot behavior is fastboot, which provides a busybox prompt in under 2 seconds. When this shell is exited the board continues on to perform a full Debian boot. This behavior is controlled by the linuxrc script, which by default is a symbolic link to linuxrc-fastboot. To automatically boot full Debian, link it instead to linuxrc-sdroot. Please note that changes made to files on the initial ramdisk are saved only in RAM. To save your changes permanently, type "save" at the fastboot prompt.

SD card features

The SD cards shipped with and for the TS-7350 contain a special four partition scheme. The first partition is a VFAT partition. On cards larger than 1GB, this partition contains Eclipse and other tools, documentation, and so forth. On cards smaller then 1GB this partition is empty. The second partition contains a raw image of the kernel to be booted on the board, while the third partition contains an initial ramdisk (initrd) which the kernel uses as its root filesystem until the fastboot shell exits. The fourth partition contains the Debian Linux distribution, and contains the root filesystem that is used when the fastboot shell exits and the full boot commences.

Board specific features

LEDs

There are three LEDs on the TS-7350: one red, one green, and one yellow. The green LED comes on at power-up and stays on by default. The green and red LEDs are controlled through the CPU GPIO port E. They can be controlled using bits 0 and 1 of the port E register at address 0x8084_0020. The yellow LED is controlled by bit 6 of the register at 0x600ff084.

Random Number Generator

The TS-7350 has a built-in true random number generator (RNG). The number is generated from internal random entropy. The 32-bit value at address 0x600f_f0d0 contains the most recent random value generated. Only thirty-two bits of true random data are created every second, so if this register is read more quickly the values read are not guaranteed to be random: in fact, you will either read the same value as previously or else a pseudo-random intermediate value from the last value generated.

40 pin general header

The general header is a 40 pin (2x7, 0.1" spacing) header providing I2C, SPI, GPIO, latched outputs, buffered inputs, A/D inputs, an external reset line, and a console UART.

The general header is made up of two adjacent headers, labeled JTAG and DIO:

2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 18 20 22 24
1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 17 19 21 23
JTAG DIO

The pins on the 40 pin header serve a variety of functions. Refer to the table below to see which pins are available for each functionality.

Pin Number Name Function
JTAG 1JTAG_DOUTReserved
JTAG 2JTAG_TMSReserved
JTAG 3GNDTied to ground
JTAG 4JTAG_DINReserved
JTAG 5HGPIO_3DIO
JTAG 6JTAG_CLKReserved
JTAG 7UART0_TXDUART0
JTAG 8UART0_RXDUART0
JTAG 9SPI_MISOSPI bus
JTAG 103.3VTied to 3.3V
JTAG 11HGPIO_5DIO
JTAG 12SPI_MOSISPI bus
JTAG 13FLASH_CS#Reserved
JTAG 14SPI_CLKSPI bus
JTAG 155VTied to 5V
JTAG 16EXT_RESET#External reset
DIO 1SPI_FRAMESPI bus
DIO 2GNDTied to ground
DIO 3RSVDReserved
DIO 4OUT_5Latched output
DIO 5IN_00Buffered input
DIO 6OUT_4Latched output
DIO 7IN_01Buffered input
DIO 8OUT_3Latched output
DIO 9IN_02Buffered input
DIO 10OUT_2Latched output
DIO 11IN_03Buffered input
DIO 12OUT_1Latched output
DIO 13IN_04Buffered input
DIO 14OUT_0Latched output
DIO 15IN_05Buffered input
DIO 16ADC4/BGPIO_7ADC/DIO
DIO 17IN_06Buffered input
DIO 18BGPIO_6DIO
DIO 19BGPIO_5DIO
DIO 20ADC2ADC/Buffered input
DIO 21I2C_SDAI2C
DIO 22ADC1ADC/Buffered input
DIO 23I2C_SCLI2C
DIO 24ADC0ADC/Buffered input

Please note:Pins labeled "reserved" are used at the factory for production purposes and should not be used for applications.

Analog to Digital Conversion

Pins labeled ADC are available for analog to digital conversion using the Cirrus 5 channel A/D converter. Channels 0, 1, 2, and 4 are available for applications. Channel 3 is used internally.

Each of these pins, if not being used for A/D conversion, can instead be used as a buffered input, or in the case of pin DIO 16, a GPIO pin. For instructions on that please refer to the relevant section below.

DIO

Pins labeled "DIO" are connected directly to EP9302 GPIO pins. To use these pins, you must first set the data direction registers, and then read or write values from the data registers. When accessing these registers, it is important to do a read-modify-write, as other bits may be used internally. Pins labeled BGPIO are accessed through port B. The port B data direction register is located at address 0x80840014 and the port B data register is at 0x80840004. Pins labeled HGPIO are accessed through port H. The port H data direction register is located at address 0x80840044 and the port H data register is at 0x80840040.

Buffered Inputs

There are a total of 10 buffered digital input lines. Pins IN_0 through IN_6 are dedicated digital inputs, while pins IN_9 through IN_11 are in parallel with analog inputs and thus can only be used for digital input if analog inputs are not needed. Pins IN_0 through IN_3 have resistor pull-ups. The others will return random data if not driven high or low.

The 32 bit register at address 0x600f_f084 provides access to digital inputs. Pins IN_0 through IN_6 are accessed by bits 7 through 13. Pin IN_9 is accessed by bit 15. Pins IN_10 and IN_11 are accessed by bits 27 and 28.

Latched Outputs

Pins OUT_0 through OUT_5 are digital output lines. The 32 bit register at address 0x600f_f084 provides access to digital outputs through bits 0 through 5.

UART0

UART0_TXD and UART0_RXD bring out the TTL level signals from the CPU. By default, this UART provides boot messages and the Linux console.

SPI Bus

The SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_FRAME pins bring out the SPI bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.

I2C Bus

The I2C_SCL and I2C_SDA pins bring out the I2C bus from the EP9302 CPU. Please refer to the EP9302 user's guide for more information.

External Reset

Driving the external reset pin low will reset the CPU. While the JFS file system on the SD card is extremely resilient and is normally not damaged by hard resets, rebooting the board using the reboot command is still recommended if the file system is mounted read/write.

Temperature Sensor (optional)

The TS-7350 has an optional on-board temperature sensor (part #:OP-TMPSENSE). The temperature sensor used is a TMP124; a copy of the datasheet can be found here, and sample code can be found here.

The temperature sensor is accessed via SPI pins on the DIO header documented in the previous section. The DATA pin on the TMP124 is connected to the SPI_MISO# signal, while the CLK pin is connected to the SPI_CLK pin. In addition there is a chip select signal which must be asserted in order to use the temperature sensor chip. This signal is accessed through bit 2 of the register at address 0x80840030. (CPU GPIO port F) Note that the polarity of this signal is active high (set this bit to select the temp sensor).

PC-104 connector

The PC-104 connector consists of 64 pins in two rows labeled A and B. The numbering of the pins in each row is shown below:

A 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
B 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

The PC-104 connector can be multiplexed between different functionalities including ISA bus and GPIO. The power-up default is GPIO mode, with all I/Os in a neutral state. To enable the PC-104 bus (ISA) signals, it is necessary to write the following values to the registers specified:

0x55555555 to address 0x600ff098
0x55555555 to address 0x600ff09c


More specifically, the functionality of the PC-104 connector can be configured in a more fine-grained manner, two pins at a time. Each pin pair will have one of four functions:

function number description
0 GPIO
1 ISA
2 reserved
3 reserved

Setting the function of each pair of pins is done by writing the function number to the appropriate pair of bits in the register corresponding to the row in question. The table below shows the bit positions in each register on the top row, while the cells below in the same column give the corresponding pin numbers for each row which are programmed with those bits at the specified register address.

row
register
adrs\/ bits->
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
A
0x600ff098
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
B
0x600ff09c
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01

For example, from the above table we can see that to set the function of pins B19 and B20 we would write the function number to bits [19:18] of the register at address 0x600ff09c. We can tell this because when we look at the "B" row we see "20 19" in the cell whose column is headed by "19 18".

The function of the PC-104 connector pins are given in the table below. The "ISA" column gives the name of the pin signal when it is configured as ISA, while the "GPIO" column gives the name of the pin signal when it is configured as GPIO. To save space, there are two sets of columns in each table, whereby the pin name is listed first, followed by the ISA signal and then the GPIO signal, and then this order is repeated for the other set of pins

pin ISA GPIO pin ISA GPIO
A1 IOCHK# A[0] B1 GND GND
A2 D7 A[1] B2 RESET B[1]
A3 D6 A[2] B3 +5V +5V
A4 D5 A[3] B4 IRQ9 B[3]
A5 D4 A[4] B5 3.3V 3.3V
A6 D3 A[5] B6 DRQ2 B[5]
A7 D2 A[6] B7 NC B[6]
A8 D1 A[7] B8 ENDX# B[7]
A9 D0 A[8] B9 8V_30V 8V_30V
A10 IORDY A[9] B10 GND GND
A11 AEN A[10] B11 MEMW# B[10]
A12 A19 A[11] B12 MEMR# B[11]
A13 A18 A[12] B13 IOW# B[12]
A14 A17 A[13] B14 IOR# B[13]
A15 A16 A[14] B15 DACK3# B[14]
A16 A15 A[15] B16 DRQ3 B[15]
A17 A14 A[16] B17 DACK1# B[16]
A18 A13 A[17] B18 DRQ1 B[17]
A19 A12 A[18] B19 RFRSH# B[18]
A20 A11 A[19] B20 BCLK B[19]
A21 A10 A[20] B21 IRQ7 B[20]
A22 A9 A[21] B22 IRQ6 B[21]
A23 A8 A[22] B23 IRQ5 B[22]
A24 A7 A[23] B24 IRQ4 B[23]
A25 A6 A[24] B25 IRQ3 B[24]
A26 A5 A[25] B26 DACK2# B[25]
A27 A4 A[26] B27 TC B[26]
A28 A3 A[27] B28 BALE B[27]
A29 A2 A[28] B29 +5V +5V
A30 A1 A[29] B30 OSC B[29]
A31 A0 A[30] B31 GND GND
A32 GND GND B32 ISA_B32 B[31]

Note: The GPIO nomenclature in these tables is such that, for example, "A[0]" means "Bit 0 of GPIO Register A", and in general "X[n]" means "Bit n of GPIO Register X" and "X[n:m]" means "Bits n through m of GPIO register X", where X is one of A or B.

PC-104 bus

The TS-7350 provides control over some of the ISA parameters of the PC-104 bus through a 32-bit register located at address 0x600ff0d4, which is defined as follows:

bit(s) function
5-0 ISA strobe length
9-6 ISA setup length
10 Honor ISA 0WS/ENDX signal (1=true)
11 TS special ISA pinout enable (1=true)
12 ISA oscillator select
0 high-jitter approximation of 14.318Mhz
1 clean 25Mhz

(Other bits in this register should be masked out.)

The ISA strobe length and ISA setup length are both given as the number of extra 10ns periods.

The ISA strobe length is the amount of additional time that ISA_IOR, ISA_IOW, ISA_MEMR, and ISA_MEMW are held asserted. The minimum (when bits are zero) is 20ns. The default power-on value is 40, for a 420ns strobe length. If configured to honor the ISA 0WS/ENDX signal, the peripheral will skip the remaining strobe time for an early transaction end, allowing for faster devices than standard ISA allows.

The ISA setup length is the additional amount of time above 20ns that the address and data are held stable before asserting the strobe. The default is 14 (160ns).

There is an additional 20ns hold time at the end of the strobe where address and data are kept valid. The default total bus cycle length is then 160ns (setup) plus 420ns (strobe) plus 20ns (hold) for a total of 500ns (2Mhz). This is very conservative for modern hardware and most designs can actually run much faster.

Bus Addresses

Pc/104 peripherals will appear in the TS-7350's physical address space in one of two address regions, depending on whether it is emulating an x86 memory cycle or I/O cycle. The base address for I/O cycles is 0x600ff800. The base address for memory cycles is 0x60002000.

GPIO on PC-104 connector

The PC-104 connector can be multiplexed between PC-104 functionality and GPIO functionality. There are up to 56 general purpose digital I/O pins available. This corresponds to 64 pins total minus 8 pins carrying power or ground rails.

Each GPIO pin has a two corresponding register bits, one in the GPIO data register, and one in the GPIO direction register. The direction register determines if the pin is an output (actively driven) or an input (tri-stated, driven externally). A high ("1") value sets a particular pin to be an output, while a low ("0") value sets it to be an input. The data register, when read, contains the current state of all pins in GPIO mode. When written, the value written will determine the state of all pins in GPIO mode, but only for pins which have their direction set to "output".

The GPIO register map follows:

address row register
0x600ff088 A data
0x600ff08c B data
0x600ff090 A direction
0x600ff094 B direction

UARTs

The TS-7350 incorporates 7 XUARTs implemented in the FPGA.  Under Linux, these are accessed through /dev/ttzn where n is the XUART # (from the table below).  The device driver name is xuart7350.   To use the UARTs on the PC104 bus, the pins must be set to GPIO functionality.  When these ports are closed, the GPIO functionality is used; when the ports are open the UART functionality overrides the GPIO functionality.

#
RS-
header
Tx / X+
Rx / X-
TxEn
0
232
COM2
TxD(3)
RxD(2)
N/A
1
232
COM1
RTS(7)
CTS(8)
N/A
2
232
COM1
DTR(4)
DCD(1)
N/A
3
485
COM2
DCD(1)
DSR(6)
auto
4
485
COM2
DTR(4)
RI(9)
auto
5
TTL
PC104
A12
A18
A13
6
TTL PC104 A15
A19(*)
A16

(*) Bit 14 of the 16-bit register at 0x600FF0D4 must be set to enable Rx on this pin.

The appropriate RS-485 option (OP-485-FD-12 or OP-485-FD-14) must be purchased with the board to use the RS-485 ports.  In full-duplex RS-485 mode, the pins for TS-UART #4 are used for Rx on TS-UART #3. To set RS-485 Full Duplex, set bit 6 of the register at address 0x600ff086.

Important Note: Due to time constraint, the TS-7350/TS-7370 boards were released while the XUART design was still in development. Because of this, some boards (those born before October 1, 2008) do not have the necessary firmware to support the XUART. There are two options to remedy this: one is to return the board to have the firmware updated. The other is to download the TS-7350/TS-7370 bitstream with XUART support and load the bitstream during the boot process. There is a writeup on considerations for loading a bitstream that can assist in this process.

The latest version of the XUART driver is available on the ftp site. Please note that this is a beta version with a few known performance issues that we are currently working to resolve.

Document History

  • 08.12.2008: Created
  • 12.17.2008: XUART #3 X+/X- were backwards