The TS-ADC24 can provide up to 8 MB/s of ADC data, but the ISA (PC/104) bus on most systems is limited to 2 MB/s bandwidth or less. So one might conclude that the TS-ADC24 is over-designed. However, the TS-ADC24 itself does not require the long ISA strobe times that typical PC/104 systems use, and a well-designed PC/104 system such as the TS-8100-4740 featuring a Spartan 6 FPGA can actually exceed 2MB/s for sustained bursts. This translates into sampling 4 ADC channels at 250 kHz or even 500 kHz. This is possible due to standard functionality in the FPGA including customizable bus timing, user DMA, and an embedded processor. With extra engineering, 1000 kHz would be possible, but this article explores what can be accomplished by a typical C programmer who does not want to venture into the realm of FPGA development.